The present invention relates to a variable frequency divider suitably adapted for a frequency synthesizer tuner of a television receiver, radio transmitter/receiver (tranceiver), etc.
FIG. 1 shows a conventional variable frequency divider which is used as a dual modulus prescaler in a frequency synthesizer tuner. FIG. 1 corresponds to, e.g., UHF programmable divider #SP8743B & M manufactured by the Plessey Company Limited (England). In FIG. 1, reference numerals 1 to 3 denote shift resisters (D flip-flops); 4 to 6 denote gate circuits; 7 denotes an expander (T flip-flop); CP denotes a clock input; and PE denotes a frequency division ratio instruction signal. This variable frequency divider operates in a well known manner; the frequency division ratio for a frequency divided output OUT with respect to an input clock CL is set to either 1/8 or 1/9 in accordance with the logic level of signal PE.
The maximum operating frequency of the variable frequency divider as shown in FIG. 1 is determined by the signal propagation time of shift registers 1 to 3 and of gate circuits 4 to 6. The maximum operating frequency of the variable frequency divider is given by: EQU 1/(.tau.D +.tau.G)
where .tau.D is a propagation delay time of the shift registers 1 to 3 and .tau.G is a propagation delay time of the gate circuits 4 to 6.
To obtain a high-speed operation of the variable frequency divider, high-speed ECL (emitter-coupled logic) shift registers of master-slave type are used for shift registers 1 to 3. The maximum operating frequency of such ECL shift registers is, at present, about 1 GHz, and that of the gate circuits is also about 1 GHz. Accordingly, the maximum operating frequency of the variable frequency divider becomes about 500 MHz. However, demand for dual modulus prescalers with still higher-speed operation and lower power consumption has become strong.